Semiconductor wafer and manufacturing method thereof

ABSTRACT

A semiconductor wafer and its manufacturing method are provided where the current driving capability of a MOS transistor can be sufficiently enhanced. An SOI layer wafer in which an SOI layer ( 32 ) is formed has a &lt;100&gt; crystal direction notch ( 32   a ) and a &lt;110&gt; crystal direction notch ( 32   b ). The SOI layer wafer and a supporting substrate wafer ( 1 ) are bonded to each other in such a way that the notch ( 32   a ) and a &lt;110&gt; crystal direction notch ( 1   a ) of the supporting substrate wafer ( 1 ) coincide with each other. When bonding the two wafers by using the notch ( 32   a ) and the notch ( 1   a ) to position the two wafers, the other notch ( 32   b ) of the SOI layer wafer can be engaged with a guide member of the semiconductor wafer manufacturing apparatus to prevent positioning error due to relative turn between the wafers. Thus an MOS transistor with a sufficiently improved current driving capability can be fabricated on the semiconductor wafer with the two wafers positioned in crystal directions shifted from each other.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor wafer and amanufacturing method thereof.

[0003] 2. Description of the Background Art

[0004] In a conventional SOI (Silicon On Insulator or Semiconductor OnInsulator) wafer, an oxide film layer resides on one main surface of asupporting substrate wafer made of, e.g. a silicon substrate, and an SOIlayer resides on the top surface of the oxide film layer. Such SOI andoxide film layers are formed by bonding to the supporting substratewafer an SOI layer wafer that has a silicon substrate with an oxide filmformed on its main surface and then removing part of it.

[0005] After the supporting substrate wafer and the SOI layer wafer arebonded together, an unwanted portion of the SOI layer wafer is removedby adopting a method such as SMART CUT (Registered Trademark) or ELTRAN(Registered Trademark); refer to Patent Document 1 shown below.

[0006] When a MOS (Metal Oxide Semiconductor) transistor is formed inthe SOI layer, it is arranged so that its channel direction is parallelto a <100> crystal direction of the SOI layer, for example. It is knownthat arranging the channel direction in parallel with <100> crystaldirection enhances the current driving capability of the P-channel MOStransistor by about 15 percent and also reduces the short-channeleffect.

[0007] It is thought that the current driving capability is enhancedbecause the hole mobility in <100> crystal direction is larger than thatin <110> crystal direction, and that the short-channel effect is reducedbecause the value of the boron diffusion coefficient in <100> crystaldirection is smaller than that in <110> crystal direction.

[0008] Now, with SOI wafers, the SOI layer wafer, in which SOI and oxidefilm layers are formed, may be bonded to the supporting substrate waferwith their crystal directions shifted at 45° (or 135°) with respect toeach other. Specifically, the two wafers are bonded together in such away that a <100> crystal direction of the SOI layer and a <110> crystaldirection of the supporting substrate wafer coincide with each other.The reason is shown below.

[0009] (100) wafers cleave along {110} crystal planes. Accordingly, whenthe SOI layer wafer and the supporting substrate wafer are bondedtogether so that the <100> crystal direction of the former coincideswith the <110> crystal direction of the latter, the wafer can becleaved, for experiments and studies, along {110} cleavage planes of thesupporting substrate wafer 1 that forms a large part of the waferthickness. On the other hand, in the SOI layer whose crystal directionis shifted, an MOS transistor can be formed so that its channeldirection is parallel with a <100> crystal direction.

[0010] Thus, when cleaved, the supporting substrate wafer 1 breaks along<110> crystal direction, while the SOI layer breaks along <100> crystaldirection. In this way, bonding the two wafers with their crystaldirections shifted from each other provides the advantage that a sectionalong the MOS transistor channel direction can be easily exposed.

[0011] The following list shows prior art reference information relatedto the present invention:

[0012] Patent Document 1: Japanese Patent Application Laid-Open No.2002-134374,

[0013] Patent Document 2: Japanese Patent Application Laid-Open No.9-153603 (1997), and

[0014] Non-Patent Publication 1: G. Scott et al., “NMOS Drive CurrentReduction Caused by Transistor Layout and Trench Isolation InducedStress,” (US), IEDM, 1999.

[0015] A conventional SOI wafer is manufactured by a method shown below,for example.

[0016] First, an SOI layer wafer and a supporting substrate wafer areprepared, both of which are a (100) wafer having a (100) plane as a mainsurface. Next, a notch (or an orientation flat) is formed at a <100>crystal direction edge of the SOI layer wafer and a notch (or anorientation flat) is formed at a <110> crystal direction edge of thesupporting substrate wafer. Then, the two substrates are bonded togetherin such a way that the <100> crystal direction of the SOI layer and the<110> crystal direction of the supporting substrate wafer coincide witheach other.

[0017] In this bonding process, the two wafers are bonded so that thenotch of the supporting substrate wafer and the notch of the SOI layerwafer coincide with each other. However, when the two wafers arepositioned by utilizing these notches only, the SOI layer <100> crystaldirection and the supporting substrate wafer <110> crystal direction maynot be precisely aligned.

[0018] With such a positioning error between wafers, the MOS transistorchannel direction cannot be precisely aligned with the SOI layer <100>crystal direction and a deviation is caused between the two. This isbecause MOS transistors are formed on the basis of the position of thesupporting substrate wafer.

[0019] Then the current driving capability of the MOS transistors cannotbe enhanced satisfactorily. Furthermore, electric characteristicvariations will occur among MOS transistors formed on the surfaces ofdifferent SOI wafers.

SUMMARY OF THE INVENTION

[0020] Accordingly, an object of the present invention is to provide asemiconductor wafer and a manufacturing method thereof in which thecurrent driving capability of a MOS transistor can be sufficientlyenhanced.

[0021] According to a first aspect of the present invention, asemiconductor wafer includes a first semiconductor wafer and a secondsemiconductor wafer.

[0022] The first semiconductor wafer has a plurality of cuts formed atedge portions in crystal directions, and the second semiconductor waferhas a cut formed at an edge portion in a crystal direction.

[0023] One of the plurality of cuts of the first semiconductor wafer andthe cut of the second semiconductor wafer are formed in differentcrystal directions. The first and second semiconductor wafers are bondedto each other with said one of the plurality of cuts of the firstsemiconductor wafer and the cut of the second semiconductor wafercoinciding with each other.

[0024] The first semiconductor wafer has a plurality of cuts and thefirst and second semiconductor wafers are bonded together in such a waythat one of the plurality of cuts of the first semiconductor wafer andthe cut of the second semiconductor wafer coincide with each other. Thatone of the plurality of cuts of the first semiconductor wafer and thecut of the second semiconductor wafer are positioned in differentcrystal directions. Thus, when the two wafers are bonded together usingthe coinciding cuts for positioning, another cut of the firstsemiconductor wafer can be engaged with a guide portion of thesemiconductor wafer manufacturing apparatus to prevent positioning errordue to relative turn between the wafers. This allows the two wafers tobe highly precisely positioned. Thus the semiconductor wafer can beeasily cleaved so that a section along MOS transistor channel directionis exposed, and a MOS transistor having a remarkably enhanced currentdriving capability can be formed on the semiconductor wafer.

[0025] According to a second aspect of the present invention, asemiconductor wafer manufacturing method includes the following steps(a) to (d). In the step (a), first and second semiconductor wafers areprepared. In the step (b), a main surface of the second semiconductorwafer is bonded to a main surface of the first semiconductor wafer. Inthe step (c), oxygen ions are implanted from the first semiconductorwafer side into a neighborhood of a part where the first and secondsemiconductor wafer are bonded to each other. In the step (d), theportion implanted with the oxygen ions is formed into an oxide filmlayer by a thermal treatment.

[0026] After the first and second semiconductor wafers are bondedtogether, oxygen ions are implanted and the oxygen-ion-implanted portionis processed into an oxide film layer through a thermal treatment. Thus,by bonding together the first and second semiconductor wafers in crystaldirections shifted from each other, it is possible to form an SOI waferthat includes an SOI layer and a supporting substrate having crystaldirections shifted with respect to each other. Furthermore, forming theoxide film layer by oxygen ion implantation and thermal process providesan SOI wafer with reduced SOI layer thickness nonuniformity. The reducedSOI layer thickness nonuniformity enhances the current drivingcapability. Thus the semiconductor wafer can be easily cleaved so that asection along the MOS transistor channel direction is exposed, and anMOS transistor having a remarkably enhanced current driving capabilitycan be formed on the semiconductor wafer.

[0027] According to a third aspect of the present invention, asemiconductor wafer manufacturing method includes the steps (a) to (e).In the step (a), a first semiconductor wafer having a plurality of cutsformed at edge portions in crystal directions is prepared. In the step(b), a second semiconductor wafer having a cut formed at an edge portionin a crystal direction that is different from the crystal direction ofone of the plurality of cuts of the first semiconductor wafer isprepared. In the step (c), the first and second semiconductor wafers arebonded to each other while using said one of the plurality of cuts ofthe first semiconductor wafer and the cut of the second semiconductorwafer in order to position the first and second semiconductor wafers,with another one of the plurality of cuts of the first semiconductorwafer being engaged with a guide portion of a semiconductor wafermanufacturing apparatus. In the step (d), oxygen ions are implanted fromthe first semiconductor wafer side into a neighborhood of a part wherethe first and second semiconductor wafers are bonded to each other. Inthe step (e), the portion implanted with the oxygen ions is formed intoan oxide film layer by a thermal treatment.

[0028] After the first and second semiconductor wafers are bondedtogether, oxygen ions are implanted and the oxygen-ion-implanted portionis processed into an oxide film layer through a thermal treatment.Accordingly, by bonding together the first and second semiconductorwafers in crystal directions shifted from each other, it is possible toform an SOI wafer that includes an SOI layer and a supporting substratehaving crystal directions shifted with respect to each other.Furthermore, forming the oxide film layer by oxygen ion implantation andthermal process provides an SOI wafer with reduced SOI layer thicknessnonuniformity. The reduced SOI layer thickness nonuniformity enhancesthe current driving capability. Thus the semiconductor wafer can beeasily cleaved so that a section along MOS transistor channel directionis exposed, and a MOS transistor having a remarkably enhanced currentdriving capability can be formed on the semiconductor wafer. Moreover,in the step (c), the first and second semiconductor wafers are bondedtogether with another one of the plurality of cuts of the firstsemiconductor wafer engaged with a guide portion of the semiconductorwafer manufacturing apparatus. This prevents positioning error due torelative turn between the wafers. Thus the two wafers can be highlyprecisely positioned and a MOS transistor with a sufficiently enhancedcurrent driving capability can be formed on the semiconductor wafer withthe two wafers bonded in different crystal directions with respect toeach other. Furthermore, electric characteristic variations are lesslikely to occur among MOS transistors formed on different semiconductorwafers.

[0029] These and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0030]FIG. 1 is the top view of a semiconductor wafer according to afirst preferred embodiment;

[0031]FIG. 2 is a cross-sectional view of the semiconductor wafer of thefirst preferred embodiment;

[0032] FIGS. 3 to 5 are cross-sectional views showing a bonding processfor forming the semiconductor wafer of the first preferred embodiment;

[0033]FIG. 6 is the top view of a semiconductor wafer manufacturingapparatus that is used in the semiconductor wafer bonding process of thefirst preferred embodiment;

[0034]FIG. 7 is a cross-sectional view of the semiconductor wafermanufacturing apparatus used in the semiconductor wafer bonding processof the first preferred embodiment;

[0035]FIG. 8 is a diagram depicting the semiconductor wafer bondingprocess of the first preferred embodiment; and

[0036] FIGS. 9 to 11 are cross-sectional views showing a semiconductorwafer manufacturing method according to a second preferred embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0037] <First Preferred Embodiment>

[0038]FIG. 1 is the top view of a semiconductor wafer according to thispreferred embodiment. This semiconductor wafer 100 is a (100) wafer thathas a (100) plane as its main surface (in FIG. 1, the circle containinga point inside represents an arrow that shows the normal direction tothe (100) plane. FIG. 2 shows the II-II section of FIG. 1.

[0039] The SOI wafer 100 includes a supporting substrate wafer 1 formedof, e.g. a silicon substrate, an oxide film layer 2 resides on one mainsurface of the supporting substrate wafer 1, and an SOI layer 32 resideson top of the oxide film layer 2. This SOI layer 32 and the oxide filmlayer 2 are formed by bonding to the supporting substrate wafer 1 an SOIlayer wafer that has a silicon substrate and an oxide film formed on itsmain surface and then removing part of it. While the SOI layer 32 andoxide film layer 2 and the supporting substrate wafer 1 generally haveapproximately the same diameter, their diameters may be somewhatdifferent from each other depending on the manufacturing process.

[0040] Semiconductor devices, including MOS transistors andinterconnections among them, are formed in the surface of the SOI layer32. The MOS transistor TR1 of FIG. 1 is an example of such asemiconductor device. In the MOS transistor TR1, “S” denotes its source,“D” denotes its drain, and “G” denotes its gate.

[0041] This MOS transistor TR1 is arranged so that its channel directionis parallel with a <100> crystal direction of the SOI layer 32.

[0042] In the semiconductor wafer 100, the supporting substrate wafer 1has a notch 1 a formed at an edge portion in a <110> crystal directionand the SOI layer 32 has a <100> crystal direction notch 32 a and a<110> crystal direction notch 32 b.

[0043] The bonding of the supporting substrate wafer and the SOI layerwafer is now described, where a SMART CUT method is shown by way ofexample.

[0044] Before bonding, the oxide film layer 2 is formed on a surface ofan SOI layer wafer 320 and a crystal defect layer DF is formed by ahydrogen ion implantation IP2 in a portion deeper than the oxide filmlayer 2 by the thickness DP1 of the SOI layer 32 (see FIG. 3).

[0045] Next, as shown in FIG. 4, the oxide film layer 2 of the SOI layerwafer 320 is bonded to a main surface of the supporting substrate wafer1. In FIG. 4, the position of the bonded plane is shown as BD. Note thatthe supporting substrate wafer 1 and the SOI layer wafer 320 are bondedso that their <100> crystal directions are at an angle of 45° or 135°with respect to each other.

[0046] Next, a thermal treatment is applied to weaken the crystal defectlayer DF and the SOI layer wafer 320 is separated at the crystal defectlayer DF as shown in FIG. 5. At this time, the peripheral portions ofthe SOI layer wafer 320, which are not bonded firmly, are also removed.FIG. 5 shows the dividing plane as DT.

[0047] Then the structure is further heat-treated to increase thebonding strength between the SOI layer 32 and the supporting substratewafer 1, and the surface of the SOI layer 32 is lightly polished toremove the residue of the crystal defect layer. The semiconductor wafer100 shown in FIGS. 1 and 2 are obtained in this way.

[0048] Next, the process of bonding the supporting substrate wafer 1 andthe SOI layer wafer 320 is described in greater detail. The bondingprocess is performed by using a semiconductor wafer manufacturingapparatus as shown in FIGS. 6 and 7, for example. FIG. 7 shows theVII-VII section of FIG. 6.

[0049] This manufacturing apparatus includes a holder HD for holding thesupporting substrate wafer 1, a wafer guide GD2 used as a guide forpositioning the SOI layer wafer 320 to be bonded, and an air pin AP forsucking and holding the semiconductor wafer. FIG. 6 shows the SOI layerwafer 320 with broken line and clearly depicts the supporting substratewafer 1 underneath.

[0050] The holder HD has a recess HL having a depth DP2, where thesupporting substrate wafer 1 is placed. A raised portion HLa is formedat the edge of the recess HL; the supporting substrate wafer 1 is placedthere with the raised portion HLa engaged with or fitted in the notch 1a.

[0051] The wafer guide GD2 is a guiding member that is situated on theholder HD to surround the recess HL. The raised portion HLa is extendedalso on the wafer guide GD2 so that it can be engaged also with thenotch 32 a of the SOI layer wafer 320.

[0052] The wafer guide GD2 includes another raised portion GD1 that canbe moved back and forth along the arrow Q shown in the drawings. Theraised portion GD1 can be moved to protrude from the wafer guide GD2toward the SOI layer wafer 320, so that it can be engaged with the <110>direction notch 32 b of the SOT layer wafer 320. The raised portion GD1and the raised portion HLa are positioned on the wafer guide GD2 at anangle of 45° with respect to each other. The raised portion GD1 issituated at a level higher than the supporting substrate wafer 1 placedin the recess HL so that it will not touch the supporting substratewafer 1 when it is moved.

[0053] When this manufacturing apparatus is used, the raised portion GD1is set in the withdrawn position in the wafer guide GD2, the supportingsubstrate wafer 1 is placed in the recess HL of the holder HD, and thenthe raised portion GD1 is moved to protrude from the wafer guide GD2.Next the SOI layer wafer 320 is carried with the air pin AP and moveddown onto the supporting substrate wafer 1 so that the notch 32 a andthe notch 32 b are engaged respectively with the raised portions HLa andGD1, and then the SOI layer wafer 320 and the supporting substrate wafer1 are bonded together. Subsequently, the raised portion GD1 is withdrawninto the wafer guide GD2 and the bonded wafers 1 and 320 are pulled upand taken out with the air pin AP.

[0054] When the depth DP2 of the recess HL is sized smaller than thethickness of the supporting substrate wafer 1, the supporting substratewafer 1 placed in the recess HL slightly protrudes above the surface ofthe holder HD. In this case, when the raised portion GD1 is moved toprotrude from the wafer guide GD2, the bottom of the raised portion GD1and the surface of the supporting substrate wafer 1 are not excessivelyspaced apart, and then the SOI layer wafer 320 can be put down whileensuring the engagement between the notch 32 b and the raised portionGD1.

[0055] During this process of bonding the two wafers, they arepositioned so that the notch 1 a of the supporting substrate wafer 1 andthe notch 32 a of the SOI layer wafer 320 coincide with each other,while the notch 32 b of the SOI layer wafer 320 is engaged with theraised portion GD1 that serves as a guide member of the semiconductorwafer manufacturing apparatus.

[0056] Note that “the notch 1 a and the notch 32 a coincide with eachother” does not mean that their shapes perfectly coincide with eachother. For example, the depths of the two notches 1 a and 32 a in thewafer radius direction may somewhat differ from each other. Also, thecentral angles of the two notches 1 a and 32 a, i.e. the angle betweenthe two sides of each “fan” shape, may somewhat differ from each other.The notch 1 a and notch 32 a work as long as their shapes coincide witheach other to such an extent that the positioning can be achievedprecisely.

[0057] Thus, the raised portion GD1 engaged with the notch 32 b limitsthe turning movement of the SOI layer wafer 320 in the wafer planedirection, which makes it possible to more effectively preventpositioning error due to relative turn between the wafers, than inconventional bonding process where wafers are positioned using only thenotches 1 a and 32 a. Thus the wafers can be highly preciselypositioned, so that an MOS transistor TR1 having a sufficiently enhancedcurrent driving capability can be formed on the semiconductor wafer,with the two wafers positioned in crystal directions shifted from eachother. Furthermore, electric characteristic variations are less likelyto occur among MOS transistors TR1 formed on different semiconductorwafers.

[0058] Note that the rest of the semiconductor wafer 100 manufacturingprocess, other than the bonding process, may be conducted by adoptingother method, such as an ELTRAN method, as well as the SMART CUT method.

[0059] This preferred embodiment thus provides a semiconductor wafer anda manufacturing method thereof in which the <100> crystal directionnotch 32 a and the <110> crystal direction notch 32 b are formed in theSOI layer wafer 320 and the two wafers 1 and 320 are bonded togetherwith the <100> crystal direction notch 32 a and the <110> crystaldirection notch 1 a of the supporting substrate wafer 1 coinciding witheach other (see FIG. 8).

[0060] As shown above, the SOI layer wafer 320 has the notches 32 a and32 b. Accordingly, while the supporting substrate wafer 1 and the SOIlayer wafer 320 are positioned by utilizing the notch 1 a of the wafer 1and the notch 32 a of the wafer 320, the notch 32 b of the SOI layerwafer 320 can be engaged with a guide member of the semiconductor wafermanufacturing apparatus to prevent positioning error between the wafersthat would be caused if the wafers turn relative to each other. Thisallows the two wafers 1 and 320 to be precisely positioned. As a result,it is easy to cleave the semiconductor wafer to expose a section alongthe MOS transistor channel direction, and it is possible to form an MOStransistor with a sufficiently enhanced current driving capability onthe semiconductor wafer.

[0061] While this preferred embodiment has shown an example in which theSOI layer wafer 320 and the supporting substrate wafer 1 are bondedtogether to form an SOI wafer, the present invention is not limited bythis example. That is to say, the present invention can be applied alsoto bulk wafers that have no oxide film layer 2. That is, the presentinvention can be applied to the formation of a bulk wafer in which twobulk wafers are bonded together with their crystal directions shiftedfrom each other, so as to form a bulk wafer whose surface crystaldirection differs from that in the deeper portion.

[0062] Also, while this preferred embodiment has shown an example inwhich notches are used to indicate crystal directions, any cuts of othershapes, such as orientation flats, may be used to show the crystaldirections.

[0063] Moreover, while this preferred embodiment has shown an example inwhich the notches 32 a and 32 b are formed in the SOI layer wafer 320respectively in <100> and <110> crystal directions, the invention is notlimited by this example. Notches 32 a and 32 b may be formed indirections other than <100> and <110> crystal directions, and they maybe positioned in other relationship with respect to each other.

[0064] <Second Preferred Embodiment>

[0065] This preferred embodiment shows a method suited to manufactureSOI wafers in which, as shown with the semiconductor wafer 100 of FIG.1, an SOI layer and a supporting substrate wafer are bonded in crystaldirections shifted from each other.

[0066] FIGS. 9 to 11 are cross-sectional views showing a semiconductorwafer manufacturing method according to this preferred embodiment.

[0067] First, an SOI layer wafer 321 and a supporting substrate wafer 1,both of which are a semiconductor wafer that has a (100) plane as a mainsurface, are prepared and bonded together in such a way that a <100>crystal direction of the SOI layer wafer 321 and a <110> crystaldirection of the supporting substrate wafer 1 coincide with each other(see FIG. 9). FIG. 9 shows the position of the bonded plane as BD. Atthis stage, no oxide film layer exists on the SOI layer wafer 321 andthe supporting substrate wafer 1.

[0068] Preferably, in this bonding process, a plurality of notches areformed on the edge of the SOI layer wafer 321 as has been shown in thefirst preferred embodiment and the two wafers are precisely positionedby using the semiconductor wafer manufacturing apparatus shown in FIGS.6 and 7. However, this preferred embodiment is not limited to thisexample.

[0069] Next, the surface of the SOI layer wafer 321 is processed bygrinding, CMP (Chemical Mechanical Polishing), chemical treatment or thelike, so as to thin the SOI layer wafer 321 to form a semiconductorlayer 322 (see FIG. 10). The thickness TH of the semiconductor layer 322may be about 100 to 1000 nm, for example.

[0070] Next, an oxygen ion implantation IP1 is applied from thesemiconductor layer 322 side into the portion where the two wafers arebonded to each other (into a neighborhood of the bonded plane BD). Thenthe structure is thermally processed at a temperature of about 1300° C.to 1400° C. to form the oxygen-ion-implanted portion into an oxide filmlayer 2. Thus the portion of the semiconductor layer 322 that is leftunoxidized forms the SOI layer 32 (see FIG. 11). The dosage of oxygenions can be 1×10¹⁷ to 1×10¹⁸ cm⁻², for example.

[0071] According to this preferred embodiment, the SOI layer wafer 321and the supporting substrate wafer 1 are bonded together with theircrystal directions shifted from each other, implanted with oxygen ions,and thermally processed to form the oxygen-ion-implanted portion intothe oxide film layer 2.

[0072] In general bonding methods, an oxide film layer is formed on asurface of one wafer and then this wafer is bonded to another wafer,without the need for oxygen ion implantation. However, nonuniformity ofthe film thickness of the SOI layer can be easily prevented by preciselycontrolling the oxygen ion implantation, so as to form a thin film withuniform thickness.

[0073] Thus, this preferred embodiment enables the manufacture of an SOIwafer that has the SOI layer 32 with reduced film thicknessnonuniformity. The reduced thickness nonuniformity of the SOI layerenhances the current driving capability. In this way, the semiconductorwafer can be easily cleaved so that a section along MOS transistorchannel direction is exposed, and a MOS transistor having a remarkablyenhanced current driving capability can be formed on the semiconductorwafer.

[0074] While the invention has been described in detail, the foregoingdescription is in all aspects illustrative and not restrictive. It isunderstood that numerous other modifications and variations can bedevised without departing from the scope of the invention.

What is claimed is:
 1. A semiconductor wafer comprising: a firstsemiconductor wafer having a plurality of cuts formed at edge portionsin crystal directions; and a second semiconductor wafer having a cutformed at an edge portion in a crystal direction; one of said pluralityof cuts of said first semiconductor wafer and said cut of said secondsemiconductor wafer being formed in different crystal directions; saidfirst and second semiconductor wafers being bonded to each other withsaid one of said plurality of cuts of said first semiconductor wafer andsaid cut of said second semiconductor wafer coinciding with each other.2. The semiconductor wafer according to claim 1, wherein an MOStransistor is formed on said first semiconductor wafer, and said MOStransistor is arranged so that its channel direction is parallel with acrystal direction of said first semiconductor wafer, and wherein saidfirst and second semiconductor wafers are bonded together with theircrystal directions shifted 45° or 135° from each other.
 3. Thesemiconductor wafer according to claim 1, wherein said semiconductorwafer has an SOI (Silicon On Insulator or Semiconductor On Insulator)structure.
 4. A semiconductor wafer manufacturing method comprising thesteps of: (a) preparing first and second semiconductor wafers; (b)bonding a main surface of said second semiconductor wafer to a mainsurface of said first semiconductor wafer; (c) implanting oxygen ionsfrom said first semiconductor wafer side into a neighborhood of a partwhere said first and second semiconductor wafers are bonded to eachother; and (d) forming the portion implanted with the oxygen ions intoan oxide film layer by a thermal treatment.
 5. The semiconductor wafermanufacturing method according to claim 4, wherein crystal directions ofsaid first and second semiconductor wafers are shifted 45° or 135° withrespect to each other.
 6. A semiconductor wafer manufacturing methodcomprising the steps of: (a) preparing a first semiconductor waferhaving a plurality of cuts formed at edge portions in crystaldirections; (b) preparing a second semiconductor wafer having a cutformed at an edge portion in a crystal direction that is different fromthe crystal direction of one of said plurality of cuts of said firstsemiconductor wafer; (c) bonding said first and second semiconductorwafers to each other while using said one of said plurality of cuts ofsaid first semiconductor wafer and said cut of said second semiconductorwafer in order to position said first and second semiconductor wafers,with another one of said plurality of cuts of said first semiconductorwafer being engaged with a guide portion of a semiconductor wafermanufacturing apparatus; (d) implanting oxygen ions from said firstsemiconductor wafer side into a neighborhood of a part where said firstand second semiconductor wafers are bonded to each other; and (e)forming the portion implanted with the oxygen ions into an oxide filmlayer by a thermal treatment.
 7. The semiconductor wafer manufacturingmethod according to claim 6, wherein said one of said cuts of said firstsemiconductor wafer and said cut of said second semiconductor wafer areformed at positions shifted 45° or 135° with respect to each other.